Invention Application
- Patent Title: SYSTEMS AND METHODS FOR PACKAGE ON PACKAGE THROUGH MOLD INTERCONNECTS
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Application No.: US14937022Application Date: 2015-11-10
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Publication No.: US20170133350A1Publication Date: 2017-05-11
- Inventor: Shubhada H. Sahasrabudhe , Sandeep B. Sane , Siddarth Kumar , Shalabh Tandon
- Applicant: Intel Corporation
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L21/56 ; H01L25/00 ; H01L23/31 ; H01L23/00

Abstract:
Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.
Public/Granted literature
- US09659908B1 Systems and methods for package on package through mold interconnects Public/Granted day:2017-05-23
Information query
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