- 专利标题: HIGH SPEED ADD-COMPARE-SELECT FOR VITERBI DECODER
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申请号: US14961228申请日: 2015-12-07
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公开(公告)号: US20170163380A1公开(公告)日: 2017-06-08
- 发明人: Yehuda AZENKOT , Bart ZEYDEL
- 申请人: Applied Micro Circuits Corporation
- 主分类号: H04L1/00
- IPC分类号: H04L1/00
摘要:
System and method of comparing-selecting state metric values for high speed. Viterbi decoding. In an Add-Compare-Select (ACS) unit, a select-control signal is produced by Boolean operations on comparator decision signals and used to control a multiplexer structure. The comparator decision signals can be generated in parallel by an array of comparators comparing all possible pairs of a set of state metrics values. The Boolean operations are predefined through Boolean algebra that uses the decision signals as variables and complies with restriction imposed by the selection criteria, e.g., to select an minimum or maximum value of the set of state metrics values. The Boolean operations are performed by a logic module implemented using basic logic gates, such as AND, OR and NOT. As a result, the multiplexer structure that receives the set of input values can output the optimum value responsive to the select control signal.
公开/授权文献
- US09948427B2 High speed add-compare-select for Viterbi decoder 公开/授权日:2018-04-17
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