A gate driving circuit includes multiple stages to provide gate signals to gate lines of a display panel. At least one stage includes first and second input circuits and output circuit, discharge circuit, pull down circuit, and hold circuit. The first input circuit delivers a (k−2)th gate signal to a first node. A second input circuit delivers a (k+1)th gate signal to the first node. The output circuit outputs a first clock signal as a k-th gate signal based on the first node. The discharge circuit discharges a second node based on the (k−2)th gate signal. The pull down circuit discharges the first node based on the second node and (k+2)th gate signal and discharges the k-th gate signal based on the second node and a (k+2)th gate signal. The hold circuit delivers a (k+3)th gate signal to the second node and maintains the signal level of the second node.