- 专利标题: ADDRESS TRANSLATION WITHIN A VIRTUALISED SYSTEM BACKGROUND
-
申请号: US15592529申请日: 2017-05-11
-
公开(公告)号: US20170344492A1公开(公告)日: 2017-11-30
- 发明人: Guillaume BOLBENES , Jean-Paul Georges PONCELET
- 申请人: ARM Limited
- 优先权: GB1609276.9 20160526
- 主分类号: G06F12/1027
- IPC分类号: G06F12/1027 ; G06F12/1009
摘要:
A memory management unit 22, 34, 48 serves to use first stage of address translation and permission data S1 managed by a guest operating system and second stage of address translation and permission data S2 managed by a hypervisor. If there is a mismatch between the permissions (or other characteristics) provided by these different translation and permission data sets, then a speculative mismatch response is triggered. This speculative mismatch response may comprise storing a virtual address to intermediate physical address mapping within a cache 32, 36 within the memory management unit. Such a cache can subsequently be accessed by an instruction seeking to determine an intermediate physical address associated with a mismatch without having to wait for a full translation (page table walk) operation to be performed.
信息查询
IPC分类: