A timing controller includes an input signal processor that receives a data enable signal and a frame frequency information signal, generates one of a first internal data enable signal having a first frame frequency and a second internal data enable signal having a second frame frequency, the first and second frame frequencies being selected based on the frame frequency information signal. A gate control signal output unit generates and outputs a first gate control signal based on the first internal data enable signal or a second gate control signal based on the second internal data enable signal. A data control signal output unit generates and outputs a first data control signal based on the first internal data enable signal or a second data control signal based on the second internal data enable signal. The pulse widths of the first and second internal data enable signals are the same.