- 专利标题: TIME-TO-DIGITAL CONVERTER AND DIGITAL PHASE LOCKED LOOP
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申请号: US15685447申请日: 2017-08-24
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公开(公告)号: US20170373698A1公开(公告)日: 2017-12-28
- 发明人: Hao YAN , Jiale Huang , Lei Lu
- 申请人: HUAWEI TECHNOLOGIES CO., LTD.
- 申请人地址: CN Shenzhen
- 专利权人: HUAWEI TECHNOLOGIES CO., LTD.
- 当前专利权人: HUAWEI TECHNOLOGIES CO., LTD.
- 当前专利权人地址: CN Shenzhen
- 主分类号: H03M1/00
- IPC分类号: H03M1/00 ; H03L7/081 ; G04F10/00
摘要:
A time-to-digital converter including N stages of converting circuits, where N≧2, and N is an integer. Each stage of converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of converting circuit outputs a delayed signal of the stage of converting circuit; and the arbiter in each stage of converting circuit receives a sampling clock and the delayed signal of the stage of converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of converting circuit. Output signals of the N stages of converting circuits form a non-linear binary number, to indicate a time difference between a clock signal and a reference signal.
公开/授权文献
- US10230383B2 Time-to-digital converter and digital phase locked loop 公开/授权日:2019-03-12