Invention Application
- Patent Title: INTEGRATED CIRCUIT LAYOUT AND METHOD OF CONFIGURING THE SAME
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Application No.: US15201200Application Date: 2016-07-01
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Publication No.: US20180006009A1Publication Date: 2018-01-04
- Inventor: Chung-Te LIN , Ting-Wei CHIANG , Hui-Zhong ZHUANG , Pin-Dai SUE , Li-Chun TIEN
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW HSINCHU
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW HSINCHU
- Main IPC: H01L27/02
- IPC: H01L27/02 ; G06F17/50 ; H01L27/092
Abstract:
An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.
Public/Granted literature
- US10269784B2 Integrated circuit layout and method of configuring the same Public/Granted day:2019-04-23
Information query
IPC分类:
