Invention Application
- Patent Title: TWO STAGE COMMAND BUFFERS TO OVERLAP IOMMU MAP AND SECOND TIER MEMORY READS
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Application No.: US15267404Application Date: 2016-09-16
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Publication No.: US20180018123A1Publication Date: 2018-01-18
- Inventor: Monish Shah , Benjamin Charles Serebrin , Albert Borchers
- Applicant: Google Inc.
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
IOMMU map-in may be overlapped with second tier memory access, such that the two operations are at least partially performed at the same time. For example, when a second tier memory read into a storage device controller internal buffer is initiated, an IOMMU mapping may be built simultaneously. To achieve this overlap, a two-stage command buffer is used. In a first stage, content is read from a second tier memory address into the storage device controller internal buffer. In a second stage, the internal buffer is written into the DRAM physical address.
Public/Granted literature
- US10296256B2 Two stage command buffers to overlap IOMMU map and second tier memory reads Public/Granted day:2019-05-21
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