• 专利标题: Phase Locked Loop Circuit With Charge Pump Up-Down Current Mismatch Adjustment And Static Phase Error Reduction
  • 申请号: US15668392
    申请日: 2017-08-03
  • 公开(公告)号: US20180048322A1
    公开(公告)日: 2018-02-15
  • 发明人: Amit Katyal
  • 申请人: Synopsys, Inc.
  • 主分类号: H03L7/089
  • IPC分类号: H03L7/089 H03L7/097 H03L7/099 H03L7/107
Phase Locked Loop Circuit With Charge Pump Up-Down Current Mismatch Adjustment And Static Phase Error Reduction
摘要:
A magnitude difference between intrinsic positive and negative current components forming a PLL's charge pump output current is determined by simultaneously outputting the intrinsic positive and negative pump current components, and incrementally increasing a bias current added to one of the intrinsic current components (e.g., such that the total positive current component is gradually increased). Calibration control voltages generated by the calibration pump output current are measured to determine when magnitudes of the adjusted (e.g., positive) current component and the non-adjusted/intrinsic (e.g., negative) current component are equal, and the bias current amount required to achieve equalization is stored as a digital converter code. During subsequent normal PLL operations, the digital converter code is utilized to control the charge pump such that the magnitude of the positive current component is adjusted by the bias current amount such that the positive and negative current components are matched.
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