A semiconductor memory device includes first wires extending in a first direction; second wires provided in a first interconnect layer including the first wires, the second wires extending in the first direction along extension lines of the first wires respectively; third wires provided in a second interconnect layer different from the first interconnect layer; and transistors on/off controlling electrical connections between the first wires and the second wires through the third wires. The first and second wires are arranged respectively in a second direction crossing the first direction. The transistors are disposed in M stages (M is integer not less than 2) in the first direction, the M stages each including a transistor array aligned in the second direction. The first second wires are periodically arranged with the minimum period including M times N first wires (N is integer not less than 2) and M times N second wires.