- 专利标题: Width Adjustment of Stacked Nanowires
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申请号: US15276372申请日: 2016-09-26
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公开(公告)号: US20180090624A1公开(公告)日: 2018-03-29
- 发明人: Kangguo Cheng , Xin Miao , Ruilong Xie , Tenko Yamashita
- 申请人: International Business Machines Corporation , Globalfoundries Inc.
- 主分类号: H01L29/786
- IPC分类号: H01L29/786 ; H01L29/06 ; H01L29/423 ; H01L29/66
摘要:
In one aspect, a method of forming a semiconductor device includes the steps of: forming an alternating series of sacrificial/active layers on a wafer and patterning it into at least one nano device stack; forming a dummy gate on the nano device stack; patterning at least one upper active layer in the nano device stack to remove all but a portion of the at least one upper active layer beneath the dummy gate; forming spacers on opposite sides of the dummy gate covering the at least one upper active layer that has been patterned; forming source and drain regions on opposite sides of the nano device stack, wherein the at least one upper active layer is separated from the source and drain regions by the spacers; and replacing the dummy gate with a replacement gate. A masking process is also provided to tailor the effective device width of select devices.
公开/授权文献
- US10069015B2 Width adjustment of stacked nanowires 公开/授权日:2018-09-04
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