- 专利标题: METHOD AND SYSTEM FOR EFFICIENT CACHE BUFFERING IN A SYSTEM HAVING PARITY ARMS TO ENABLE HARDWARE ACCELERATION
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申请号: US15335030申请日: 2016-10-26
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公开(公告)号: US20180113633A1公开(公告)日: 2018-04-26
- 发明人: Horia Simionescu , Timothy Hoglund , Sridhar Rao Veerla , Panthini Pandit , Gowrisankar Radhakrishnan
- 申请人: Avago Technologies General IP (Singapore) Pte. Ltd.
- 主分类号: G06F3/06
- IPC分类号: G06F3/06 ; G06F12/0871
摘要:
A system and method for efficient cache buffering are provided. The disclosed method includes receiving a host command from a host, extracting command information from the host command, determining an Input/Output (I/O) action to be taken in connection with the host command, determining that the I/O action spans more than one strip, and based on the I/O action spanning more than one strip, allocating a cache frame anchor for a row on-demand along with a cache frame anchor for a strip to accommodate the I/O action.
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