Invention Application
- Patent Title: STACKED TRANSISTORS WITH DIFFERENT CHANNEL WIDTHS
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Application No.: US15463155Application Date: 2017-03-20
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Publication No.: US20180122703A1Publication Date: 2018-05-03
- Inventor: KANGGUO CHENG , LAWRENCE A. CLEVENGER , BALASUBRAMANIAN S. PRANATHARTHIHARAN , JOHN ZHANG
- Applicant: International Business Machines Corporation
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L27/088 ; H01L29/06 ; H01L29/66
Abstract:
A semiconductor device includes a first gate stack arranged about a first nanowire and a second nanowire, the first nanowire is arranged above a second nanowire, the first nanowire is connected to a first source/drain region and a second source/drain region. A second gate stack is arranged about a third nanowire and a fourth nanowire, the third nanowire is arranged above a fourth nanowire, the third nanowire is connected to a third source/drain region and a fourth source/drain region. An insulator layer having a first thickness is arranged adjacent to the first gate stack.
Public/Granted literature
- US10354921B2 Stacked transistors with different channel widths Public/Granted day:2019-07-16
Information query
IPC分类:
