Invention Application
- Patent Title: METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING A PATTERNED METAL LAYER EMBEDDED IN AN INTERLAYER DIELECTRIC LAYER
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Application No.: US15863986Application Date: 2018-01-08
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Publication No.: US20180130742A1Publication Date: 2018-05-10
- Inventor: Ching-Ling Lin , Chih-Sen Huang , Ching-Wen Hung , Jia-Rong Wu , Tsung-Hung Chang , Yi-Hui Lee , Yi-Wei Chen
- Applicant: UNITED MICROELECTRONICS CORP.
- Priority: CN201410430805.X 20140828
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L27/06 ; H01L23/532 ; H01L21/768 ; H01L21/8234

Abstract:
A method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (STI) in the substrate, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask as mask are utilized to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess and on the STI.
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Information query
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