Invention Application
- Patent Title: SEQUENTIAL DATA WRITES TO INCREASE INVALID TO MODIFIED PROTOCOL OCCURRENCES IN A COMPUTING SYSTEM
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Application No.: US15352272Application Date: 2016-11-15
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Publication No.: US20180137053A1Publication Date: 2018-05-17
- Inventor: Pavel I. Kryukov , Stanislav Shwartsman , Joseph Nuzman , Alexandr Titov
- Applicant: INTEL CORPORATION
- Main IPC: G06F12/0808
- IPC: G06F12/0808 ; G06F12/0811 ; G06F12/0837 ; G06F12/084 ; G06F12/0842 ; G06F12/0891

Abstract:
An example system on a chip (SoC) includes a cache, a processor, and a predictor circuit. The cache may store data. The processor may be coupled to the cache and store a first data set at a first location in the cache and receive a first request from an application to write a second data set to the cache. The predictor circuit may be coupled to the processor and determine that a second location where the second data set is to be written to in the cache is nonconsecutive to the first location, where the processor is to perform a request-for-ownership (RFO) operation for the second data set and write the second data set to the cache.
Public/Granted literature
- US10133669B2 Sequential data writes to increase invalid to modified protocol occurrences in a computing system Public/Granted day:2018-11-20
Information query
IPC分类: