- 专利标题: INSTRUCTION AND LOGIC TO EXPOSE ERROR DOMAIN TOPOLOGY TO FACILITATE FAILURE ISOLATION IN A PROCESSOR
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申请号: US15372734申请日: 2016-12-08
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公开(公告)号: US20180165144A1公开(公告)日: 2018-06-14
- 发明人: Ashok RAJ , Narayan RANGANATHAN , Mohan J. KUMAR , Vincent J. ZIMMER
- 申请人: INTEL CORPORATION
- 主分类号: G06F11/07
- IPC分类号: G06F11/07 ; G06F9/30
摘要:
A processor includes an instruction decoder to receive an instruction to perform a machine check operation, the instruction having a first operand and a second operand. The processor further includes a machine check logic coupled to the instruction decoder to determine that the instruction is to determine a type of a machine check bank based on a command value stored in a first storage location indicated by the first operand, to determine a type of a machine check bank identified by a machine check bank identifier (ID) stored in a second storage location indicated by the second operand, and to store the determined type of the machine check bank in the first storage location indicated by the first operand.
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