Invention Application
- Patent Title: REDUCING BANDWIDTH CONSUMPTION WHEN PERFORMING FREE MEMORY LIST CACHE MAINTENANCE IN COMPRESSED MEMORY SCHEMES OF PROCESSOR-BASED SYSTEMS
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Application No.: US15426473Application Date: 2017-02-07
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Publication No.: US20180225224A1Publication Date: 2018-08-09
- Inventor: Richard Senior , Christopher Edward Koob , Gurvinder Singh Chhabra , Andres Alejandro Oportus Valenzuela , Nieyan Geng , Raghuveer Raghavendra , Christopher Porter , Anand Janakiraman
- Applicant: QUALCOMM Incorporated
- Main IPC: G06F12/128
- IPC: G06F12/128 ; G06F12/02

Abstract:
Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems is disclosed. In this regard, a memory system including a compression circuit is provided. The compression circuit includes a compress circuit that is configured to cache free memory lists using free memory list caches comprising a plurality of buffers. When a number of pointers cached within the free memory list cache falls below a low threshold value, an empty buffer of the plurality of buffers is refilled from a system memory. In some aspects, when a number of pointers of the free memory list cache exceeds a high threshold value, a full buffer of the free memory list cache is emptied to the system memory. In this manner, memory access operations for emptying and refilling the free memory list cache may be minimized.
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Information query
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