Invention Application
- Patent Title: SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
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Application No.: US15888944Application Date: 2018-02-05
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Publication No.: US20180286952A1Publication Date: 2018-10-04
- Inventor: Yuya ABIKO , Natsuo YAMAGUCHI , Satoshi EGUCHI
- Applicant: Renesas Electronics Corporation
- Priority: JP2017-069688 20170331
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L29/78 ; H01L29/739 ; H01L29/16 ; H01L21/265 ; H01L21/02 ; H01L29/06 ; H01L29/40 ; H01L21/308 ; H01L29/66
Abstract:
In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.
Information query
IPC分类:
