A gate integrated driving circuit for a display panel. The gate integrated driving circuit may comprise N reset circuits. For each of the N reset circuits, a first terminal thereof may be coupled to a reference signal terminal a second terminal thereof may be coupled to signal output terminals of a set of input and output circuits respectively, a third terminal thereof may be coupled to control terminals of driving circuits of the set of input and output circuits respectively, and a fourth terminal thereof may be coupled to a clock signal terminal coupled to input terminals of the driving circuits of the set of input and output circuits respectively. N may be an integer of at least 3. The set of input and output circuits may contain two or more input and output circuits.