- 专利标题: STEP HEIGHT REDUCTION OF MEMORY ELEMENT
-
申请号: US15663671申请日: 2017-07-28
-
公开(公告)号: US20180351099A1公开(公告)日: 2018-12-06
- 发明人: Jen-Sheng YANG , Wen-Ting CHU , Chih-Yang CHANG , Chin-Chieh YANG , Kuo-Chi TU , Sheng-Hung SHIH , Yu-Wen LIAO , Hsia-Wei CHEN , I-Ching CHEN
- 申请人: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 申请人地址: TW Hsinchu
- 专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 当前专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 当前专利权人地址: TW Hsinchu
- 主分类号: H01L45/00
- IPC分类号: H01L45/00 ; H01L27/24
摘要:
A semiconductor device includes an inter-metal dielectric layer, a memory cell, a transistor and a dielectric layer. The memory cell includes a metal-insulator-metal (MIM) structure over a top surface of the inter-metal dielectric layer. The transistor underlies the inter-metal dielectric layer. The dielectric layer extends over the transistor and along the top surface of the inter-metal dielectric layer. The dielectric layer is separated from the MIM structure.
公开/授权文献
- US10158072B1 Step height reduction of memory element 公开/授权日:2018-12-18
信息查询
IPC分类: