- 专利标题: SINGLE CLOCK SOURCE FOR A MULTIPLE DIE PACKAGE
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申请号: US15952169申请日: 2018-04-12
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公开(公告)号: US20190041895A1公开(公告)日: 2019-02-07
- 发明人: Yingyu Miao , Gerald Pasdast , Peipei Wang , Mahesh Kumashikar
- 申请人: Yingyu Miao , Gerald Pasdast , Peipei Wang , Mahesh Kumashikar
- 主分类号: G06F1/10
- IPC分类号: G06F1/10 ; H03K5/15 ; H01L23/66 ; H01L25/065
摘要:
A processing device includes a package, a plurality of dies disposed on the package, where each die comprises a clock receiver, and a single common clock source to generate a common clock signal. The processing device also includes a clock distribution circuitry coupled to the single common clock source. The clock distribution circuitry distributes the common clock signal from the single common clock source to each of the plurality of dies individually. The clock distribution circuitry includes a first group of terminated transmission lines. The first group of terminated transmission lines includes a first terminated transmission line, a second terminated transmission line, and a first termination resistor coupled between the first terminated transmission line and the second terminated transmission line. The first terminated transmission line and the second terminated transmission line receive the common clock signal from the single common clock source.
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