A circuit arrangement, a signal processor, and a method of interleaved switched boundary mode power conversion are disclosed. The circuit arrangement comprises at least an input for receiving an input voltage from a power supply; an output to provide an output voltage to a load; a first interleaved circuit comprising a first energy storage device and a first controllable switching device; one or more secondary interleaved circuits, each comprising a secondary energy storage device, and a secondary controllable switching device; and a signal processor, connected to the controllable switching devices. The signal processor comprises a first switching cycle controller, configured for cycled zero-current switching operation of the first controllable switching device; and one or more secondary switching cycle controllers, configured for cycled zero-current switching operation of the secondary controllable switching devices. The signal processor is configured to control, in a given switching cycle, an on-time period of each of the secondary controllable switching devices to correspond to an on-time period of the first controllable switching device. The signal processor is further configured to control phases between the on-time periods of the first and the one or more secondary switching controllers, so that the on-time periods are distributed over the given switching cycle to reduce an overall current ripple at the input.