发明申请
- 专利标题: Methods of Manufacturing an Integrated Circuit Having Stress Tuning Layer
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申请号: US16390877申请日: 2019-04-22
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公开(公告)号: US20190252328A1公开(公告)日: 2019-08-15
- 发明人: Shin-Puu Jeng , Clinton Chao , Szu-Wei Lu
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 主分类号: H01L23/00
- IPC分类号: H01L23/00 ; H01L23/52 ; H01L21/56 ; H01L21/78 ; H01L21/302 ; H01L21/02 ; H01L21/3205 ; H01L21/306 ; H01L21/304
摘要:
Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.
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