• Patent Title: PREFORMED INTERLAYER CONNECTIONS FOR INTEGRATED CIRCUIT DEVICES
  • Application No.: US16316528
    Application Date: 2016-09-26
  • Publication No.: US20190295943A1
    Publication Date: 2019-09-26
  • Inventor: Elliot N. TAN
  • Applicant: Intel Corporation
  • International Application: PCT/US2016/053830 WO 20160926
  • Main IPC: H01L23/522
  • IPC: H01L23/522 H01L21/768
PREFORMED INTERLAYER CONNECTIONS FOR INTEGRATED CIRCUIT DEVICES
Abstract:
A first metallization layer is deposited on a first insulating layer on a substrate. The first metallization layer comprises a set of first conductive lines. A second metallization layer is deposited over the first metallization layer. The second metallization layer comprises a set of second conductive lines that cross the set of first conductive lines to form intersection regions. At least one of the intersection regions comprises a first portion of one of the first conductive lines and a second portion of one of the second conductive lines that crosses the first portion. A plurality of preformed connections are disposed between the first metallization layer and the second metallization layer at the plurality of intersection region. At least one of the preformed connections comprises a second insulating layer aligned to the second portion and the first portion.
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