A MOS device has a reduced ON-resistance; the MOS device has a first lightly doped diffusion (LDD) region which is longer than a second LDD region thereof, and the impurity concentration of the second LDD region is higher than that of the first LDD region. Another MOS device has a spacer layer on a drain sidewall of the gate but does not have a spacer layer on a source sidewall of the gate, wherein the drain sidewall is a sidewall of the gate conductive layer that is adjacent to the drain, and the source sidewall is a sidewall of the gate conductive layer that is adjacent to the source. The MOS device has a higher breakdown voltage, lower ON-resistance, and mitigates the threshold voltage roll-off and other short channel effects.