Passivating silicide-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. Each of the plurality of conductive lines is recessed relative to an uppermost surface of the ILD layer. A metal silicide layer is on the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the metal silicide layer and on the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a portion of the metal silicide layer on one of the plurality of conductive lines.