Invention Application
- Patent Title: MULTILAYER INTERCONNECT STRUCTURE WITH BURIED CONDUCTIVE VIA CONNECTIONS AND METHOD OF MANUFACTURING THEREOF
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Application No.: US16153905Application Date: 2018-10-08
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Publication No.: US20200111680A1Publication Date: 2020-04-09
- Inventor: Raymond Albert Fillion , Kaustubh Ravindra Nagarkar
- Applicant: General Electric Company
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L23/498 ; H01L25/00 ; H01L23/538

Abstract:
An electronics package includes a multilayer interconnect structure comprising insulating substrate layers and conductor layers. The electronics package also includes an electrical component comprising I/O pads electrically coupled to the conductor layers and conductive through vias extending through at least two insulating substrate layers and electrically connected to at least a portion of the I/O pads. The conductor layers include a first conductor layer including a ground plane buried in the multilayer interconnect structure, the ground plane forming direct electrical and physical connections with a conductive through via electrically connected to a ground I/O pad of the plurality of I/O pads. The conductor layers also include a second conductor layer including a power plane buried in the multilayer interconnect structure, the power plane forming direct electrical and physical connections with a conductive through via that is electrically connected to a power I/O pad of the plurality of I/O pads.
Public/Granted literature
Information query
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