Invention Application
- Patent Title: MEMORY SYSTEM WITH DYNAMIC CALIBRATION USING A TRIM MANAGEMENT MECHANISM
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Application No.: US16775099Application Date: 2020-01-28
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Publication No.: US20200168282A1Publication Date: 2020-05-28
- Inventor: Michael Sheperek , Larry J. Koudele , Steve Kientz
- Applicant: Micron Technology, Inc.
- Main IPC: G11C16/26
- IPC: G11C16/26 ; G06F3/06

Abstract:
A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to iteratively: calibrate read levels based on associated read results, wherein the read levels are tracked via optimization target data that at least initially includes at least one read level in addition to a target trim; and remove a calibrated read level from the optimization target data when the calibrated read level satisfies a calibration condition.
Public/Granted literature
- US11177006B2 Memory system with dynamic calibration using a trim management mechanism Public/Granted day:2021-11-16
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