An LC oscillator architecture in which an LC tank is driven by a negative resistance element (amplifier) including first and second Vbe/Vgs multipliers cross-coupled to the LC tank. Each Vbe/Vgs multiplier circuitry including a transistor with a control terminal as a negative input, a reference terminal as a positive input, and an output terminal, a shunt resistance connected between the control terminal and the reference terminal, a series resistance connected between the control terminal and the output terminal for one of the same transistor or the other transistor, and a shorting capacitance connected between the control terminal of the transistor, and the output terminal of the transistor of the other Vbe/Vgs multiplier. An example application is an LC VCO, such as for a PLL, CDR, or retimer.