Invention Application
- Patent Title: TRANSACTION NESTING DEPTH TESTING INSTRUCTION
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Application No.: US16651045Application Date: 2018-08-21
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Publication No.: US20200257551A1Publication Date: 2020-08-13
- Inventor: Grigorios MAGKLIS , Matthew James HORSNELL , Stephan DIESTELHORST
- Applicant: Arm Limited
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@40128ea5
- International Application: PCT/EP2018/072560 WO 20180821
- Main IPC: G06F9/46
- IPC: G06F9/46 ; G06F9/38 ; G06F9/30 ; G06F11/36

Abstract:
In a system providing transactional memory support, a transaction nesting depth testing instruction is provided for triggering processing circuitry to set at least one status value to one of a plurality of states depending on a transaction nesting depth indicative of a number of executed transaction start instructions of a given thread for which the corresponding transaction remains unaborted and uncommitted, the plurality of states including a first state selected when the transaction nesting depth is and at least one further state selected when the transaction nesting depth is greater than or less than. The ISA supported enables the setting of the at least one status value and a conditional branch conditional on the at least one status value being in the first state to be performed in response to a single transaction nesting depth testing instruction and a single conditional branch instruction.
Public/Granted literature
- US11775297B2 Transaction nesting depth testing instruction Public/Granted day:2023-10-03
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