- 专利标题： MULTI-LAYER BARRIER FOR CMOS UNDER ARRAY TYPE MEMORY DEVICE AND METHOD OF MAKING THEREOF
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申请号： US16860358申请日： 2020-04-28
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公开(公告)号： US20200258909A1公开(公告)日： 2020-08-13
- 发明人: Fumitaka AMANO
- 申请人： SANDISK TECHNOLOGIES LLC
- 主分类号： H01L27/11582
- IPC分类号： H01L27/11582 ; H01L29/45 ; H01L21/768 ; H01L23/485 ; H01L21/265 ; H01L27/11568 ; H01L27/11521 ; H01L27/11526 ; H01L27/11573 ; H01L29/167 ; H01L27/11556
摘要：
A semiconductor structure includes a doped semiconductor material portion, a metal-semiconductor alloy portion contacting the doped semiconductor material portion, a device contact via structure in direct contact with the metal-semiconductor alloy portion, and at least one dielectric material layer laterally surrounding the device contact via structure. The device contact via structure includes a barrier stack and a conductive fill material portion. The barrier stack includes at least two metal nitride layers and at least one nitrogen-containing material layer containing nitrogen and an element selected from silicon or boron.
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