Invention Application
- Patent Title: LOW POWER SIGNALING INTERFACE
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Application No.: US16828591Application Date: 2020-03-24
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Publication No.: US20200294557A1Publication Date: 2020-09-17
- Inventor: Frederick A. Ware , John Eric Linstadt , Carl W. Werner
- Applicant: Rambus Inc.
- Main IPC: G11C7/04
- IPC: G11C7/04 ; G06F1/12 ; G11C7/22 ; G11C29/02 ; G11C29/50 ; H03K5/15 ; H01L39/22

Abstract:
In a chip-to-chip signaling system includes at least one signaling link coupled between first and second ICs, the first IC has an interface coupled to the signaling link and timed by a first interface timing signal. The second IC has an interface coupled to the signaling link and timed by a second interface timing signal that is mesochronous with respect to the first interface timing signal. The second IC further has phase adjustment circuitry that adjusts a phase of the second interface timing signal using a digital counter implemented with Josephson-junction circuit elements.
Public/Granted literature
- US11450356B2 Synchronous signaling interface with over-clocked timing reference Public/Granted day:2022-09-20
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