Invention Application
- Patent Title: PREDICTING LOCAL LAYOUT EFFECTS IN CIRCUIT DESIGN PATTERNS
-
Application No.: US16427321Application Date: 2019-05-30
-
Publication No.: US20200380088A1Publication Date: 2020-12-03
- Inventor: Jing Sha , Dongbing Shao , Yufei Wu , Zheng Xu
- Applicant: International Business Machines Corporation
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06N20/00 ; G06N3/08 ; G06N3/04 ; G06K9/62

Abstract:
A method for predicting local layout effect in a circuit design pattern includes obtaining a plurality of circuit design patterns, generating layout images from the circuit design patterns, extracting feature vectors from the layout images by processing the layout images in a computer vision machine learning algorithm, comparing the feature vector extracted from a selected layout image to clusters of feature vectors extracted from the layout images, wherein the clusters of feature vectors include an in-range cluster and an outlier cluster, and labelling a circuit design pattern corresponding to the selected layout image, for which threshold voltage has not been experimentally measured, as being an in-range circuit design pattern or an outlier circuit design pattern, in response to the selected layout image respectively correlating with the in-range cluster or with the outlier cluster.
Public/Granted literature
- US10831976B1 Predicting local layout effects in circuit design patterns Public/Granted day:2020-11-10
Information query