A logic circuit comprising a logic sub-circuit arranged to output a stream, S1, of Fresnel lens values, F(x), of a Fresnel lens for display on [m×n] pixels of a pixelated display device. In a first step, the logic circuit is arranged to set an initial data value stored in a first data register unit of the logic sub-circuit to (a−k)2 and set an initial data value stored in a second data register unit of the logic sub-circuit to a2−(a−k)2. In a second step the logic circuit is arranged to read the initial data value stored in the first data register unit and the initial data value stored in the second data register unit in a first iteration, and to read the data value stored in the first data register unit in the preceding iteration and the data value stored in the second data register unit in the preceding iteration, in a further iteration. In a third step, the logic circuit is arranged to sum the data value read from the first data register unit and the data value read from the second data register unit to form x2. In a fourth step, the logic circuit is arranged to calculate F(x) based on x2. In a fifth step, the logic circuit is arranged to output F(x) as the next value in the stream of F(x) values. In a sixth step, the logic circuit is arranged to write x2 to the first data register unit. In a seventh step, the logic circuit is arranged to add 2k2 to the value stored in the second data register unit. In an eighth step, the logic circuit is arranged to perform further iterations that repeat the second to seventh steps for x=a+k, a+2k, a+3k . . . a+(n−1)k, wherein a is the starting value of x, k is an increment in x and F(a) is the first value of stream, S1.