Invention Application
- Patent Title: PEAK AND AVERAGE CURRENT REDUCTION FOR SUB BLOCK MEMORY OPERATION
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Application No.: US16832293Application Date: 2020-03-27
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Publication No.: US20210304822A1Publication Date: 2021-09-30
- Inventor: Yu-Chung Lien , Sarath Puthenthermadam , Huai-Yuan Tseng
- Applicant: SanDisk Technologies LLC
- Applicant Address: US TX Addison
- Assignee: SanDisk Technologies LLC
- Current Assignee: SanDisk Technologies LLC
- Current Assignee Address: US TX Addison
- Main IPC: G11C16/26
- IPC: G11C16/26 ; G11C16/04

Abstract:
A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells arranged in strings and connected to word lines overlying one another in a stack. The block is divided into first and second sub-blocks programmed as a whole in a sub-block mode and includes a particular group connected to a particular word line. A control circuit determines whether the particular group being read is in the second sub-block when operating in the sub-block mode. The control circuit also determines whether one of the first and second sub-blocks is not programmed based on whether the particular group being read is in the second sub-block. The control circuit applies an adjusted read voltage to the word lines of the one of the first and second sub-blocks while reading the particular group based on whether the one of the first and second sub-blocks is not programmed.
Public/Granted literature
- US11189351B2 Peak and average current reduction for sub block memory operation Public/Granted day:2021-11-30
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