A memory sub-system includes a memory sub-system controller comprising at least one host channel, a memory device comprising a plurality of memory die, and at least one input/output (I/O) expander circuit coupled between the at least one host channel of the memory sub-system controller and to the memory device to connect the plurality of memory die to the memory sub-system controller. The at least one I/O expander circuit is to limit an impedance load presented on the at least one host channel to an impedance load of a corresponding subset of the plurality of memory die selected during a given time period.