Disclosed is a memory device, which includes a memory cell, a bit line connected to the memory cell, a controller that generates at least one current control code, a first current generator that generates a first current having a proportional to absolute temperature (PTAT) characteristic, based on the at least one current control code from the controller, a second current generator that generates a second current having a complementary to absolute temperature (CTAT) characteristic, based on the at least one current control code from the controller, a subtractor that generates a third current by subtracting the second current from the first current, and a sense amplifier that controls a load current to be supplied to the bit line based on the third current, and generates a bit line compensation current for compensating for a leakage current of the bit line.