Invention Application
- Patent Title: BITLINE STRUCTURE FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME
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Application No.: US17032944Application Date: 2020-09-25
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Publication No.: US20220102357A1Publication Date: 2022-03-31
- Inventor: Sang-Yun Lee
- Applicant: Sang-Yun Lee
- Applicant Address: US OR Hillsboro
- Assignee: Sang-Yun Lee
- Current Assignee: Sang-Yun Lee
- Current Assignee Address: US OR Hillsboro
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L29/78 ; H01L29/66

Abstract:
The invention involves a method of manufacturing a bonded semiconductor structure, comprising providing a support substrate which carries a transistor, and providing an interconnect region earned by the support substrate. The interconnect region includes a first multiple bypass bitline having an upper bypass interconnect and upper bypass via. The method includes providing a first conductive bonding layer carried by the interconnect region, wherein the first conductive bonding layer is connected to the upper bypass interconnect through the upper bypass via, and providing a vertical transistor carried by the first conductive bonding layer, the vertical transistor being in communication with the transistor through the interconnect region. The first multiple bypass bitline reduces the impedance experienced by the vertical transistor.
Public/Granted literature
- US11424248B2 Bitline structure for three-dimensional integrated circuit and method of forming the same Public/Granted day:2022-08-23
Information query
IPC分类: