Invention Application
- Patent Title: METHOD FOR MANUFACTURING A WAFER LEVEL CHIP SCALE PACKAGE (WLCSP)
-
Application No.: US17483076Application Date: 2021-09-23
-
Publication No.: US20220122941A1Publication Date: 2022-04-21
- Inventor: Chun Yi TENG , David GANI
- Applicant: STMicroelectronics PTE LTD
- Applicant Address: SG Singapore
- Assignee: STMicroelectronics PTE LTD
- Current Assignee: STMicroelectronics PTE LTD
- Current Assignee Address: SG Singapore
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/768 ; H01L21/78

Abstract:
Trenches are opened from a top surface of a production wafer that extend down through scribe areas to a depth that is only partially through a semiconductor substrate. Prior to performing a bumping process, a first handle is attached to the top surface of the production wafer. A back surface of the semiconductor substrate is then thinned to reach the trenches and form a wafer level chip scale package at each integrated circuit location delimited by the trenches. A second handle is then attached to a bottom surface of the thinned semiconductor substrate, and the first handle is removed to expose underbump metallization pads at the top surface. The bumping process is then performed to form a solder ball at each of the exposed underbump metallization pads.
Public/Granted literature
- US11908831B2 Method for manufacturing a wafer level chip scale package (WLCSP) Public/Granted day:2024-02-20
Information query
IPC分类: