A stage circuit including: a first sub-stage circuit coupled to a first input terminal receiving an input signal, a second input terminal receiving a first clock signal, and a third input terminal receiving a second clock signal, the first sub-stage circuit controlling a voltage of a first node, a second node, and a third node based on the input signal and the first and second clock signals, and supplying a first scan signal to a first output terminal based on the voltage of the second and third nodes; and a second sub-stage circuit coupled to the second input terminal, a fourth input terminal receiving a third clock signal, and the first and second nodes, the second sub-stage circuit supplying a second scan signal to a second output terminal based on the first and third clock signal, and the voltage of the first and second nodes.