Invention Application
- Patent Title: INTEGRATED CIRCUIT
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Application No.: US17571365Application Date: 2022-01-07
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Publication No.: US20220132500A1Publication Date: 2022-04-28
- Inventor: Takashi IWAI , Daichi IMAMURA , Tomofumi TAKATA , Yoshihiko OGAWA
- Applicant: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
- Applicant Address: US CA Torrance
- Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
- Current Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
- Current Assignee Address: US CA Torrance
- Priority: JP2007-160348 20070618
- Main IPC: H04W72/04
- IPC: H04W72/04 ; H04J13/00 ; H04J13/22

Abstract:
It is an object to provide a sequence allocating method that, while maintaining the number of Zadoff-Chu sequences to compose a sequence group, is configured to make it possible to reduce correlations between different sequential groups. This method comprises the steps of setting a standard sequence with a standard sequence length and a standard sequence number in a step, setting a threshold value in accordance with an RB number in a step, setting a sequence length corresponding to RB number in a step, judging whether ¦r/N−rb/Nb¦=Xth(m) is satisfied in a step, including a plurality of Zadoff-Chu sequences with a sequence number and a sequence length in a sequence group in a step if the judgment is positive, and allocating the sequence group to the same cell in a step.
Public/Granted literature
- US11711791B2 Integrated circuit Public/Granted day:2023-07-25
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