Invention Application
- Patent Title: Trust-Region Method with Deep Reinforcement Learning in Analog Design Space Exploration
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Application No.: US17495489Application Date: 2021-10-06
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Publication No.: US20220138570A1Publication Date: 2022-05-05
- Inventor: Chia-Yu Tsai , Hung-Hao Shen , Chen-Feng Chiang , Chung-An Wang , Yiju Ting , Chia-Shun Yeh , Chin-Tang Lai , Feng-Ming Tsai , Kai-En Yang
- Applicant: MediaTek Inc.
- Applicant Address: TW Hsinchu
- Assignee: MediaTek Inc.
- Current Assignee: MediaTek Inc.
- Current Assignee Address: TW Hsinchu
- Main IPC: G06N3/08
- IPC: G06N3/08

Abstract:
A system performs the operations of a neural network agent and a circuit simulator for analog circuit sizing. The system receives an input indicating a specification of an analog circuit and design parameters. The system iteratively searches a design space until a circuit size is found to satisfy the specification and the design parameters. In each iteration, the neural network agent calculates measurement estimates for random sample generated in a trust region, which is a portion of the design space. Based on the measurement estimate, the system identifies a candidate size that optimizes a value metric. The circuit simulator receives the candidate size and generates a simulation measurement. The system calculates updates to weights of the neural network agent and the trust region for a next iteration based on, at least in part, the simulation measurement.
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