Invention Application
- Patent Title: CLOCK SELF-TESTING METHOD AND ASSOCIATED CIRCUIT
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Application No.: US17507419Application Date: 2021-10-21
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Publication No.: US20220146576A1Publication Date: 2022-05-12
- Inventor: Changxian Zhong
- Applicant: Chengdu Monolithic Power Systems Co., Ltd.
- Applicant Address: CN Chengdu
- Assignee: Chengdu Monolithic Power Systems Co., Ltd.
- Current Assignee: Chengdu Monolithic Power Systems Co., Ltd.
- Current Assignee Address: CN Chengdu
- Priority: CN202011265341.3 20201112
- Main IPC: G01R31/3185
- IPC: G01R31/3185

Abstract:
A clock self-testing method and circuit. The clock self-testing method includes introducing a first clock signal and a second clock signal, counting cycles of the first clock signal and the second clock signal respectively beginning at the same moment, and if one of the number of cycles of the first clock signal being counted and the number of cycles of the second clock signal being counted is equal to N, determining whether the remained number of cycles is in a count range from M to N. If the remained number of cycles is out of the count range from M to N, the first clock signal and the second clock signal have errors.
Public/Granted literature
- US11609271B2 Clock self-testing method and associated circuit Public/Granted day:2023-03-21
Information query
IPC分类: