Invention Application
- Patent Title: Through Wafer Trench Isolation and Capacitive Coupling
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Application No.: US17583322Application Date: 2022-01-25
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Publication No.: US20220148912A1Publication Date: 2022-05-12
- Inventor: Scott Robert Summerfelt , Thomas Dyer Bonifield , Sreeram Subramanyam Nasum , Peter Smeys , Benjamin Stassen Cook
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L49/02 ; H01L27/12 ; H01L23/544 ; H01L23/00 ; H01L21/78

Abstract:
In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.
Public/Granted literature
- US12148717B2 Through wafer trench isolation between transistors in an integrated circuit Public/Granted day:2024-11-19
Information query
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