Invention Application
- Patent Title: SEMICONDUCTOR PACKAGE UTILIZING A HYBRID BONDING PROCESS AND METHOD OF MANUFACTURING THE SAME
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Application No.: US17367005Application Date: 2021-07-02
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Publication No.: US20220157779A1Publication Date: 2022-05-19
- Inventor: JIHOON KIM
- Applicant: SAMSUNG ELECTRONICS CO., LTD,
- Applicant Address: KR Suwon-Si
- Assignee: SAMSUNG ELECTRONICS CO., LTD,
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD,
- Current Assignee Address: KR Suwon-Si
- Priority: KR10-2020-0151642 20201113
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/31 ; H01L23/48

Abstract:
A semiconductor package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a peripheral region having a groove and a bonding region that is disposed higher than the groove. The second semiconductor chip is disposed in the bonding region of the first semiconductor chip. The second semiconductor chip is directly electrically connected to the first semiconductor chip. The second semiconductor chip includes an overhang protruded from the bonding region. The overhang is spaced apart from a bottom surface of the groove. Thus, a bonding failure, which may be caused by particles generated during a cutting the wafer and adhered to the edge portion of the second semiconductor chip, between the first semiconductor chip and the second semiconductor chip might be avoided.
Public/Granted literature
- US11855044B2 Semiconductor package utilizing a hybrid bonding process and method of manufacturing the same Public/Granted day:2023-12-26
Information query
IPC分类: