A semiconductor device according to an embodiment of the present disclosure includes: a conductive region, an end region positioned at a portion where the conductive region ends, and a connection region positioned between the conductive region and the end region. The conductive region includes: an n+ type substrate; an n− type layer positioned at the first surface of the n+ type substrate; and a p type region positioned on the n− type layer, and a gate electrode that fills an inside of a trench penetrating the p type region and positioned in the n− type layer, and a side wall of the trench positioned at the portion where the conductive region ends is inclined.