A gate driving circuit includes a first gate driving circuit and a second gate driving circuit, wherein the m number of first clock signals input to the first gate driving circuit includes an (n+1)-th clock signal and an (n+k)-th clock signal, and the m number of second clock signals input to the second gate driving circuit includes an (n+2)-th clock signal and an (n+k+1)-th clock signal, where the n is any integer, and the k is a natural number of 3 or more, a high level voltage duration of the (n+1)-th clock signal and a high level voltage duration of the (n+k)-th clock signal do not overlap, and a high level voltage duration of the (n+2)-th clock signal and a high level voltage duration of the (n+k+1)-th clock signal do not overlap.