Invention Application
- Patent Title: MITIGATING COOLDOWN PEELING STRESS DURING CHIP PACKAGE ASSEMBLY
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Application No.: US17139313Application Date: 2020-12-31
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Publication No.: US20220208693A1Publication Date: 2022-06-30
- Inventor: Mukta Ghate Farooq , Katsuyuki Sakuma , Krishna R. Tunga , Hilton T. Toy
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/367 ; H01L23/373 ; H01L23/31 ; H01L21/48 ; H01L21/56

Abstract:
A lidded chip package apparatus has reduced latent thermal stress in an under-chip high-CTE layer of the chip package because the lid of the package was adhered to a substrate of the package and cured during a same thermal excursion as when underfill was dispensed and cured under a chip of the package, and the chip package was cooled from the combined underfill and lidding process to room temperature with the lid adhered to the chip and the substrate, thereby reducing latent thermal stress in the under-chip high-CTE layer of the chip package.
Public/Granted literature
- US11545444B2 Mitigating cooldown peeling stress during chip package assembly Public/Granted day:2023-01-03
Information query
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