Invention Application
- Patent Title: SEMICONDUCTOR PACKAGE INCLUDING POST
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Application No.: US17479042Application Date: 2021-09-20
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Publication No.: US20220246568A1Publication Date: 2022-08-04
- Inventor: Jaekul LEE , Hyungsun JANG , Gayoung KIM , Minjeong SHIN
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR SUWON-SI
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR SUWON-SI
- Priority: KR10-2021-0013152 20210129
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/10

Abstract:
A semiconductor package includes a lower redistribution layer disposed on a lower surface of the semiconductor chip including an insulating laver, a redistribution pattern, a via, an under bump metal (UBM), and a post disposed on the redistribution pattern. The post vertically overlaps with the UBM. A mold layer is on the lower redistribution layer and surrounds the semiconductor chip. A connecting terminal is connected to the UBM. The UBM includes a first section contacting the redistribution pattern, and a second section contacting the insulating layer. The lost has a ring shape having an inner surface and an outer surface when viewed a top view. A maximum width of the inner surface is less than a Maximum width of an upper surface of the first section. A maximum width of the outer surface is greater than the maximum width of the upper surface of the first section.
Public/Granted literature
- US11967578B2 Semiconductor package including post Public/Granted day:2024-04-23
Information query
IPC分类: