A variable resistance memory device includes a memory cell structure on a substrate, the memory cell structure including conductive layers, each of the conductive layers including conductive lines spaced apart from each other in a direction parallel to a top surface of the substrate, and memory cell arrays alternatingly stacked with the conductive layers in a first direction perpendicular to a top surface of the substrate, a first peripheral circuit layer between the substrate and the memory cell structure, the first peripheral circuit layer including first transistors, and a second peripheral circuit layer between the first peripheral circuit layer and the memory cell structure, the second peripheral circuit layer including second transistors, and the second transistors including core transistors that are connected to corresponding ones of the conductive lines.